Lauterbach supports Latest Synopsys ASIP Designer Tool

Hoehenkirchen, Germany - September 3, 2024 - Lauterbach's TRACE32® tools now offer interoperability with the latest Synopsys ASIP Designer™ tool for designing application-specific instruction-set processors (ASIPs) and programmable accelerators. TRACE32 support includes debugging the ASIP cores on a hardware implementation or in the Synopsys instruction-set simulator.

Lauterbach extends support for its industry-leading TRACE32® debug and trace tools to application-specific instruction-set processors created with the V-2024.06 release of Synopsys’ ASIP Designer tool.

Synopsys' ASIP Designer tool accelerates the design of application-specific instruction-set processors (ASIPs) and programmable accelerators. ASIP Designer's language-based approach automatically generates synthesizable RTL and software development kits (SDKs) from a single architectural specification, significantly reducing processor design and verification efforts. ASIPs are used in a wide range of signal-processing intensive applications, including wireless base stations, mobile phones, audio processing, image processing, and cloud computing.

Synopsys and Lauterbach engineering teams worked closely together to implement TRACE32 support. The result is an API that allows TRACE32 PowerView software to access ASIP Designer’s instruction-set simulators and disassemblers, as well as the actual hardware implementation of the ASIP that is generated by ASIP Designer on an FPGA or ASIC. TRACE32 and the API can support the broad architectural scope of ASIP Designer, from specialized scalar processors to very-long instruction-word (VLIW) and wide vector processors.

The TRACE32® tools consist of the universal PowerView debug and trace software and debug and trace accelerator modules. While Lauterbach's intelligent PowerDebug modules offer the fastest download speeds and shortest response times for efficient debugging and test automation, the PowerTrace real-time trace modules provide complete insight into what the CPUs and other cores of an embedded system are doing without affecting its real-time performance in any way. Trace analysis, including code coverage measurements, can help bring embedded designs to market faster, safer, and more reliably.

TRACE32® enables simultaneous debugging and tracing of the CPU and other cores in an SoC, a unique capability that covers the entire system. It does not matter whether the system is SMP (symmetric multiprocessing), AMP (asymmetric multiprocessing), or iAMP (integrated asymmetric multiprocessing). Lauterbach's innovative iAMP debug and trace technology enables debugging of multicore systems with identical CPU instruction sets in a single TRACE32® PowerView GUI.

"Working with Synopsys' latest version of ASIP Designer, our TRACE32 tools can now also be used to debug custom processors implementing ASIP instruction-set architectures and peripherals for almost any application," said Stephan Lauterbach, founder and CTO of Lauterbach GmbH. "This applies to the entire lifecycle from simulator to real silicon."

"Synopsys ASIP Designer gives users the ability to speed development of custom processors with the best power, performance and area for their specific applications," said Mick Posner, vice president of IP product management at Synopsys. "The collaboration between Synopsys and Lauterbach enables software developers to accelerate their innovation and optimize embedded software to create highly differentiated products."

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詳細は http://www.lauterbach.com/ をご覧ください。

プレス問い合わせ

Evi Ederer, Lauterbach GmbH

Altlaufstraße 40, 85635 Höhenkirchen-Siegertsbrunn

電話 +49 (8102) 9876 182

E-Mail:press@lauterbach.com