ウェビナー
RISC-V System Debug and Analysis Made Easy with Lauterbach TRACE32® and Siemens Tessent Embedded Analytics
Processor trace gives software developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. In this presentation, Siemens and Lauterbach will give an overview of how processor trace can be used to improve embedded software and applications. We will explain the RISC-V Efficient Trace (E-trace) specification and cover the capabilities of the combined RISC-V debug and trace solution based on the Tessent Embedded Analytics and TRACE32® debug and trace tools including a demonstration. The presenters will be available for live Q&A at the end of the webinar.
Siemens is a key contributor to the RISC-V Efficient trace specification. Lauterbach is the leading supplier of debug and trace tools for embedded systems and key contributor to the RISC-V debug and trace standards. The presentation will include a demonstration of the combined solution, which shows the efficient and simple debugging and tracing of even heterogeneous, complex RISC-V based chips.
Who should attend
- SoC Architects
- Software Architects
- 組込みソフトウェアエンジニア
- Anyone considering or already using RISC-V
何が学べるか
- What the RISC-V Efficient trace (E-trace) standard is and how it reduces some of the risks of adopting RISC-V
- How the non-intrusive visibility that it provides can be used to understand program behavior for advanced debugging and code optimization
- How the Tessent Enhanced Trace Encoder is part of a complete SoC debug solution
- How to use Lauterbach’s TRACE32® Debug and Trace tools in order to gain extensive insight into a RISC-V SoC with Tessent Embedded Analytics
